AIGOR: One FPGA Neuromorphic Architecture That Runs Any Spiking Neural Network

Running spiking neural networks (SNNs) on hardware has always meant picking your poison: either you use a dedicated neuromorphic chip locked to one neuron model, or you build a custom FPGA accelerator that only works for the exact network you designed it around. A research team has introduced AIGOR, a modular, event-driven neuromorphic architecture that breaks that trade-off. By making the neuron model, numeric precision, and network topology all configurable at instantiation time rather than hard-coded at design time, AIGOR lets the same FPGA fabric run radically different SNN workloads without a redesign. That matters for anyone prototyping neural inference on AMD, Xilinx, or similar platforms.

What Is the Core Finding?

AIGOR proves that a single configurable architecture can faithfully reproduce two completely different SNN workloads on the same hardware cores, matching reference accuracy and spike-level precision in both cases.

The two test workloads were intentionally chosen to stress different aspects of SNN inference. The first was a feedforward image classifier trained in snnTorch, a popular Python SNN framework. The second was a recurrent balanced random network modeled in NEST, a neuroscience simulator used for large-scale brain modeling. Getting both to work on identical hardware cores, with results that match their software references, is a meaningful proof of configurability rather than just a claim.

The prototype ran on the AMD Versal VPK180, a high-end adaptive SoC that combines programmable logic with AI engines. The multi-core synchronization scheme was validated in simulation up to one thousand cores arranged on a three-dimensional torus topology, which gives a sense of how far the architecture is intended to scale.

How Does It Work Technically?

AIGOR organizes neurons into timestep-synchronized processing cores that pass spike data as packets over a packet-switched communication layer, similar in spirit to how network-on-chip designs route data between processing elements on an FPGA.

The key engineering decision is that the architecture is assembled from a library of parameterized IP blocks covering compute, memory, and communication, rather than being a one-off design. A single declarative specification file drives the generation of cores, neuron kernels, and synaptic memory images for a given network. That means changing the neuron model or remapping neurons onto hardware cores is a configuration step, not a full redesign. The folding ratio (how many neurons are time-multiplexed onto one hardware core) and the partitioning across cores are both set per instance.

Spike events propagate as packets between cores, which is the event-driven part of the title. Rather than updating every neuron every clock cycle regardless of activity, the system only processes neurons when spikes arrive. This is the same efficiency argument that makes biological neural computation attractive for low-power inference applications.

What Does This Mean for FPGA and Embedded Engineers?

If you have been experimenting with SNNs on an FPGA, you have probably hit the wall where every new network topology requires reworking the accelerator from scratch. AIGOR's approach of separating the architecture from the network specification is a practical step toward reusable neuromorphic IP.

The validation across two FPGAs with the recurrent network matching its NEST reference at spike-level precision is particularly relevant. It means the synchronization and communication scheme is robust enough to split a network across multiple devices, which opens up larger models than a single chip can hold. For embedded engineers interested in neuromorphic inference at the edge, a configurable multi-chip architecture that does not require a custom chip tape-out is worth watching.

The snnTorch integration also matters. snnTorch has become one of the more accessible on-ramps for engineers experimenting with SNNs in Python. If a trained snnTorch model can be deployed to this architecture without retraining or manual hardware translation, the workflow gap between simulation and deployment shrinks considerably.

What Are the Current Limits?

The researchers are transparent about where the prototype falls short. Post-implementation measurements identified two bottlenecks: the synaptic-delivery datapath (the path that retrieves synaptic weights and delivers them to neurons when a spike arrives) and the global timestep barrier (the synchronization point where all cores must agree a timestep is complete before advancing).

Both bottlenecks are understood well enough that the team describes a set of datapath refinements currently in development. Because the architecture is configurable rather than monolithic, those refinements can be applied as changes to the existing core library rather than requiring a ground-up redesign. The one-thousand-core torus validation was also done in simulation rather than on physical hardware, so real-world scaling behavior at that size remains to be demonstrated.

As configurable neuromorphic architectures like AIGOR mature and their IP libraries become available to the broader FPGA community, the gap between training an SNN in software and deploying it on programmable hardware could close in a way that finally makes edge neuromorphic inference practical for everyday embedded projects.