NEMESIS Uses LLMs to Generate Fast, SPICE-Verified Amplifier Equations

Analog circuit design has always been a bottleneck. When you are tuning an operational transconductance amplifier (OTA) for a mixed-signal project, you are stuck choosing between slow, accurate SPICE simulations and fast but rough hand calculations. A new framework called NEMESIS offers a third path: using large language models to generate analytical performance equations that are then verified and corrected against real SPICE results, hitting under 7% average error while running more than 4600 times faster than full SPICE evaluation.

What Is the Core Finding?

NEMESIS generates compact, SPICE-anchored equations for OTA circuits directly from a netlist and schematic, using an LLM as the starting engine and SPICE as the error-correction referee. The result is a symbolic model that is fast enough for rapid design exploration but accurate enough to trust.

The key insight is that neither pure analytical modeling nor pure simulation alone is the right tool. Analytical models are lightning fast but drift from reality as process corners shift. Full SPICE is the ground truth but costs enormous compute time per evaluation. NEMESIS sits in between, producing equations that have been iteratively corrected until they agree with SPICE within tight tolerances across a defined biasing range.

How Does It Work Under the Hood?

The framework takes an OTA netlist and schematic as inputs, identifies circuit primitives such as differential pairs and current mirrors, and then asks an LLM to write initial performance equations for gain, bandwidth, and related parameters. If NEMESIS has seen a structurally similar OTA before, it reuses equations from that prior run as a head start.

Those initial equations are then fed into a SPICE-based repair loop. The framework simulates the circuit, compares the equation output against the SPICE result, and feeds the discrepancy back to the LLM so it can revise the equations. This loop repeats until the error falls below the target threshold. Once converged, the final equations can be evaluated almost instantly, which is where the reported 4622x speedup comes from. The framework was validated on five different OTA topologies inside a commercial 65nm process design kit.

What Does This Mean for Analog and Mixed-Signal Engineers?

If you are designing analog front ends, sensor interfaces, or data converters on an ASIC or even on a custom FPGA platform with integrated analog blocks, the ability to explore design space with near-SPICE accuracy at a fraction of the simulation cost is genuinely useful. Running thousands of design-space evaluations during optimization becomes tractable when each evaluation takes microseconds instead of minutes.

The framework also has a reuse angle that matters in practice. Once NEMESIS has built verified equations for a given OTA topology, those equations serve as a starting point for future runs on similar circuits. Teams maintaining a library of standard analog cells could build up a growing collection of pre-verified models, reducing cold-start time on new projects significantly.

What Are the Current Limits?

The paper demonstrates NEMESIS on five OTA topologies in a single 65nm commercial process. That is a meaningful proof of concept, but it leaves open questions about how well the approach generalizes to more exotic topologies, different process nodes, or circuit classes beyond OTAs such as bandgap references or switched-capacitor filters.

The under-7% average relative error figure is promising for early-stage design exploration, but it may not be tight enough for final sign-off on precision analog blocks where even small gain or offset errors matter. The SPICE repair loop also still requires SPICE access during the equation-generation phase, so the speedup is most relevant after convergence, during the iterative design optimization stage rather than at initial model creation. Engineers working without access to a commercial PDK SPICE setup would not be able to run the repair loop as described.

As LLMs continue to improve their understanding of circuit topology and symbolic mathematics, frameworks like NEMESIS point toward a future where analog design iteration happens at the speed of digital synthesis.