Weave Converts SPICE Netlists to Schematics With 100% Verified Accuracy

If you have ever run a SPICE simulation or exported a netlist from a machine-learning tool, you know the frustration: you get a text file full of component connections, but no diagram you can actually read and reason about. A new tool called Weave solves this by converting those netlists directly into LTspice schematics, and it does something no existing tool could claim before: it proves, automatically, that every schematic it produces is electrically identical to the original netlist.

What Is the Core Finding?

Weave achieves 100% verified connectivity on a standard 117-circuit benchmark, compared to 76% for the best competing approach. It does this deterministically, without any machine learning, and runs entirely in the browser as a single file with no dependencies.

The comparison point here is Schemato, a state-of-the-art large language model based converter that reports a graph-edit-distance similarity score rather than a hard correctness guarantee. On the same public test set, Schemato compiled 76% of circuits and scored 0.35 on similarity. Weave compiled all 117 and verified exact connectivity on all 117. That gap is not incremental improvement, it is a fundamentally different class of result.

The key distinction is that Weave produces a binary correctness certificate instead of a similarity score. After generating the schematic, Weave re-parses it back into a netlist and compares it net-for-net against the original input. If they match exactly, the result is marked correct. If they do not, the result is flagged as a failure rather than reported as probably-okay.

How Does It Work Technically?

Weave uses a Sugiyama-style layered graph layout, a classical algorithm from graph drawing research that organizes nodes into horizontal layers and minimizes edge crossings. This gives the generated schematic a structured, readable appearance rather than a tangled mess of wires.

To place components correctly in LTspice's .asc schematic format, Weave needs to know where each component's pins are located relative to its symbol. The tool embeds a pin table covering 5,093 LTspice symbols, meaning it can handle the vast majority of parts you would encounter in real analog and mixed-signal designs. On the larger Analog Devices LTspice demo collection of 3,460 circuits, Weave verified exact connectivity for 88.4% of them. The remaining failures were concentrated in dense multi-pin power modules, a specific and well-understood edge case rather than a general failure mode.

What Does This Mean for Embedded and Analog Engineers?

For anyone working with LTspice on analog design, this changes how you can interact with simulation outputs. Circuits generated programmatically, exported from another tool, or produced by an AI assistant can now be converted into a readable, verified schematic automatically.

The practical workflow benefit is significant. If you are writing scripts to generate SPICE netlists parametrically, perhaps sweeping component values across a filter design or generating variants of a power supply topology, you can now convert each variant directly into a schematic you can inspect visually. The round-trip verification means you do not have to manually audit the output for wiring errors. The tool also runs client-side as a single dependency-free file, so there is no server, no API key, and no installation pipeline to manage.

For anyone feeding netlists through machine learning pipelines, this also addresses a real safety gap. Learning-based tools can silently introduce connectivity errors, and a similarity score of 0.35 gives you no clear threshold for when to trust the output. A binary pass-or-fail certificate does.

What Are the Current Limits?

The 88.4% success rate on the larger Analog Devices corpus is strong but not perfect. The failures are concentrated in dense multi-pin power modules, which suggests the pin table or layout algorithm struggles with parts that have many closely spaced pins in non-standard arrangements.

The tool is also currently tied to LTspice's .asc format specifically. If your workflow uses KiCad, ngspice, or another simulator's schematic format, Weave does not directly help yet. The underlying approach, layered graph layout plus round-trip verification, could in principle be extended to other formats, but that work is not described in this paper. The benchmark circuits also come from LTspice itself, so the tool has been validated most thoroughly in the environment it was designed for.

As deterministic, verifiable schematic generation becomes a standard expectation rather than a nice-to-have, tools like Weave point toward a future where AI-generated circuit designs can be trusted by construction rather than spot-checked by hand.